1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device incorporating a bonding pad arrangement which is suited both to a package specification which requires lead terminals to be provided only on one side of a package and to a package specification which requires the lead terminals to be provided on both of two opposing sides of a package.
2. Description of the Related Art
FIG. 1A shows a known semiconductor device which was reported at the Spring Meeting of 1988 All Japan Conference of Electro-Communication Engineering. This semiconductor device has a semiconductor substrate 1 which is provided with a plurality of bonding pads B arranged along both longitudinal sides thereof. Numeral 3 denotes a plurality of circuit regions provided on the semiconductor substrate 1. FIG. 1B is a fragmentary plan view of the semiconductor substrate 1, having the bonding pads arranged along longitudinal sides thereof, mounted on a 20-pin SOJ (Small Outline J-leaded Package), while FIG. 1C shows the same semiconductor substrate 1 mounted on a 20-pin ZIP (Zig-zag In-line Package). In case of a 4M-bit dynamic RAM, a specification requires that the width W of the 20-pin SOJ 2 is 350 mil, i.e., about 8.9 mm as shown in FIG. 2A, and that the height H of the 20-pin ZIP 9 is 400 mil, i.e., about 10.16 mm, as shown in FIG. 2B.
Referring to FIG. 1B, the bonding pads 4a to 4e and 6a to 6e of the semiconductor substrate 1 mounted on the SOJ 2 are connected to leads 7 formed on the package, through bonding wires 8. In this case, the semiconductor substrate 1 can be received in the SOJ 2 of the described specification without difficulty.
In the case of the package shown in FIG. 1C, however, it is necessary that the elongated leads 7a to be connected with the bonding pads 4a to 4e be provided along that longitudinal side of the ZIP 9 where no lead is led out therefrom. Since the size of the package is predetermined as stated above, the length l of the shorter sides of the rectangular semiconductor substrate 1 must be undesirably reduced in order to provide a sufficient area for arrangement of the elongated leads 7a. For instance, in the case of a 4M-bit dynamic RAM, it is necessary that a capacitor having a capacitance of at least 30 femtofarad be provided in each memory cell in order to eliminate troubles such as a soft error thereby attaining high reliability. For this reason, the memory cell is required to have a size which is about 5 .mu.m in length and about 2 .mu.m in width. Under the conditions were the length l of the shorter sides of the semiconductor substrate 1 is restricted, the width, i.e., the length of shorter sides, of the memory cell is further restricted with the result that a high precision processing is required.
In order to overcome the above-described problems shown in FIG. 1, a semiconductor device has been proposed in which at least two bonding pads for the same signal are provided on the periphery of a semiconductor substrate 1 in a spaced relation, as shown in FIG. 3A. More specifically, referring to this Figure, a first bonding pad 10a for a signal A0, a bonding pad 10b for a signal Al, a bonding pad 10c for a signal A2, and other bonding pads are arranged along a shorter side of the semiconductor substrate 1 at a suitable interval. In addition, a second bonding pad 10d for the signal A0 is provided on the longitudinal side of the semiconductor substrate 1. The first bonding pad 10a for the signal A0 and the second bonding pad 10d for the same signal A0 are connected to each other through internal wiring 11. The point of connection between the first and second bonding pads 10a and 10d is connected to a buffer circuit 12 provided on the semiconductor substrate 1.
FIG. 3B is a fragmentary plan view of an arrangement in which the semiconductor device 1 of FIG. 3A is encapsulated in a ceramic package 13. Terminals such as a terminal 14a for a signal A0, a terminal 14b for a signal A1, a terminal 14c for a signal A2 and other terminals are arranged along a shorter side of the ceramics package 13 at suitable intervals. The first bonding pad 10a for the signal A0 is connected to the terminal 14a through a bonding wire 15a. Similarly, bonding wires 15b and 15c are used for providing connection between the bonding pads 10b, 10c for the signals A1, A2 and corresponding terminals 14b and 14c. Thus, only the first bonding pad 10a for the signal A0 is used for the receiving of the signal A0, while the second bonding pad 10d for the signal A0 is not used. The terminals 14a, 14b and 14c for the signals A0, A1 and A2 are respectively connected to pins (not shown) which are exposed on the outer surface of the ceramics package 13 for receiving external signals.
FIG. 3C is a fragmentary plan view showing the structure obtained by encapsulating the semiconductor device of FIG. 3A in a plastic molded package 20. Terminals such as a terminal 16a for a signal A0, a terminal 16b for a signal A1, a terminal 16c for a signal A2 are arranged at suitable intervals on the plastic molded package 20 surrounding the semiconductor substrate 1. The second bonding pad 10d for the signal A0 is connected to the terminal 16a through a bonding wire 15a. Similarly, bonding wires 15b and 15c are used to provide respective connections between the bonding pads 10b, 10c for the signals A1, A2 and corresponding terminals 16b, 16c. In this case, second bonding pad 10d for the signal A0 is used for receiving the signal A0, and the first bonding pad 10a for the signal A0 does not take part in receiving that signal. The terminals 16a, 16b and 16c are connected to pins which are exposed on the outer surface of the plastic mold package 20 for receiving external signals.
In each of the arrangements shown in FIGS. 3A and 3B, one of two bonding pads for the same signal is selectively used according to the type of the package in which the semiconductor substrate is encapsulated, thus offering an advantage that the wire bonding between the bonding pads on the semiconductor substrate and the corresponding terminals on the package is facilitated.
The semiconductor device of the type described encounters a problem in that, since a pair of bonding pads for the same signal are always connected with each other for the external signal A0, the input capacity of the semiconductor device as viewed from the external signal input pin is increased, often to exceed the allowable limit. A semiconductor device disclosed in Japanese Published Patent Application No. 62-244144 has been proposed for the purpose of overcoming the above-described problem. Referring to FIG. 4 which is a circuit diagram showing the construction of this semiconductor device, a semiconductor substrate 1 carries first and second bonding pads 10a and 10d for the signal A0, an internal buffer circuit 12, a bonding pad 30 for a power supply, a bonding pad 31 for switching and a switch circuit 39. The bonding pad 30 for power supply is bonded to a power supply terminal (not shown) of a voltage Vcc which is provided on the package at the time of packaging of the semiconductor substrate 1 and the bonding pad 31 for switching is disposed in the vicinity of the bonding pad 30 for power supply. The switch circuit 39 includes an N-channel MOS transistor 34, inverters 32, 33, P-channel MOS transistors 35, 38, and N-channel MOS transistors 36, 37.
The operation of this semiconductor device is as follows. In the case where the power supply terminal on the package is not connected to the bonding pad 31 for switching, a node A is always held at the ground potential, i.e., at a low level, because the N channel MOS transistor 34 conducts. For the same reason, nodes B and C are maintained at high and low levels, respectively. Therefore, the P-channel MOS transistor 35 and the N-channel MOS transistor 36 become conductive, while the N-input channel MOS transistor 37 and the P-channel MOS transistor 38 become non-conductive, so that the first bonding pad 10a for the signal A0 is connected to the internal buffer circuit 12, while the second bonding pad 10d is separated from the internal buffer circuit 12.
On the other hand, in the case where the power supply terminal on the package is bonded to the bonding pad 30 for a power supply by means of a bonding wire 41 and also to the bonding pad 31 for switching through a bonding wire 42, the node A is forcibly set at a high level, while the node B and the node C are set to low and high levels, respectively. In consequence, the P-channel MOS transistor 35 and the N-channel MOS transistor 36 becomes non-conductive, while the N-channel MOS transistor 37 and the P-channel MOS transistor 38 become conductive, with the result that the first bonding pad 10a for the signal A0 is isolated from the internal buffer circuit 12 while the second bonding pad 10d for the signal A0 is connected to the internal buffer circuit 12.
Thus, only one of the first and second bonding pads 10a and 10d for the signal A0 is selectively connected to the internal buffer circuit 12, while the other bonding pad is isolated from the internal buffer circuit 12, depending on whether the power supply terminal on the package is connected to the bonding pad 31 for switching. With the arrangement shown in FIG. 4, therefore, despite the fact that a pair of bonding pads are provided on the semiconductor substrate 1 for the same signal, the input capacity as viewed from the external signal input pin can be reduced almost to the same level as that obtained when only one bonding pad for the external signal is provided on the semiconductor substrate 1.
FIG. 5A shows a 4M-bit dynamic RAM as an example of a semiconductor memory device which incorporates a bonding pad change-over means of the type described hereinabove. This 4M-bit dynamic RAM can be used either as a dynamic RAM of 4 M words.times.1 bit type or a dynamic RAM of 1 M words.times.4 bits type. The switching between these two modes is effected depending upon, for example, whether or not a signal is input to a bonding pad for switching (not shown).
Arrangements obtained by mounting the semiconductor substrate 1 on an SOJ 2 in both of these two modes are respectively shown in FIGS. 5B and 5C. More specifically, FIG. 5B shows an arrangement in which the semiconductor device is used as a dynamic RAM of 4 M words.times.1 bit type, while FIG. 5C shows an arrangement in which the semiconductor device is used as a dynamic RAM of 1 M words .times.4 bits type.
In each of the arrangements shown in FIGS. 5B and 5C, the design is such that bonding pads A9a and A9b receive the same signal and switching means of the type explained in connection with FIG. 4 is used to realize either the arrangement of FIG. 5B in which the bonding pad A9b is used for the connection or the arrangement of FIG. 5C in which the bonding pad A9a is used for the connection. Unfortunately, however, the arrangements of the type described in connection with FIGS. 5A to 5C cannot give a satisfactory solution to, the problem explained before in connection with FIG. 1C, i.e., the undesirable restriction on the area of the semiconductor substrate 1 encountered when the semiconductor substrate 1 is packaged in a ZIP.
FIG. 6A shows another known semiconductor substrate 1 which disclosed in Japanese Published Patent Application No. 62-122139. Referring to this Figure, bonding pads 50a and 50b correspond to one signal, while bonding pads 51a and 51b correspond to another signal. One of the bonding pads 50a and 50b and one of the bonding pads 51a and 51b are selected by switching means of the type shown in FIG. 4. FIGS. 6B and 6C show arrangements which are obtained by packaging the semiconductor substrate 1 of FIG. 6A in a ZIP 9 and in a DIP (Dual In-line Package) 53, respectively. As will be understood from these Figures, the semiconductor substrate 1 of the type shown in FIG. 6A is suitable for packaging in a ZIP or a DIP, but is not suitable for packaging in an SOJ. Namely, as shown in FIG. 6D, when the semiconductor substrate of the type shown in FIG. 6A is packaged in an SOJ 2, the area of the semiconductor substrate 1 is undesirably restricted since the areas each having a length d sufficient to arrange elongated leads 7a are required in both ends of the package. As a result extremely precise and delicate processing is required.